The present invention relates generally to semiconductor devices, and, more particularly, to input/output (I/O) pad structure for 3D integrated circuit (IC).
A semiconductor IC chip communicates with the outside world through various I/O pads, such as signal pads, and power/ground (P/G) pads. FIG. 1 is a cross-sectional view of a conventional I/O pad structure 100, which is formed in an exemplary 7-metal, circuit-under-pad (CUP) process. An I/O cell structure 120 including metal 1 through metal 5 as interconnect is formed on top of a substrate 110. The I/O cell structure 120 can be any circuit as only two top metal layers, metal 6 (134) and metal 7 (136) are used in this case for the pad structure 130. Metal 7 (136) is connected to metal 6 (134) by vias 144. Metal 6 (134) are connected to the I/O cell 120 by vias 142. A bonding wire is then attached to the metal 7 (136). The I/O cell structure 120, for inputting and/or outputting signals and for receiving power and ground supplies, typically includes semiconductor devices such as transistors and resistors. Such semiconductor devices may be used in input buffers, output drivers or electrostatic discharge (ESD) circuits. In general, the semiconductor devices are considered to involve active area, as electrical conductivity in these area, unlike in metals, is semi-conductive, i.e., in between that of a conductor and that of an insulator.
However, the I/O pad structure 100 is developed for single chip packaging technology. As three-dimensional (3D) integrated circuit (IC) is gaining popularity, I/O pad structures should be able to fit the new 3D IC technology.
FIG. 2 is a cross-sectional view of an exemplary 3D IC pad structure 200. Two dies 210 and 230 are stacked face-to-face in order to save space. The bottom die 210 comprises a substrate 212 and an inter-connector 218 connecting the substrate 212 to a Cu-bond 221 through a dielectric material 215. Semiconductor devices, such as transistors, are formed in the substrate 212. The inter-connector 218 may include multiple metal layers, vias and contacts (not shown). A via connects two metal layers. A contact connects a metal layer to the substrate 212. The Cu-bond 221 is a metal surface for making connection with a Cu-bond 241 on the top die 230. The top die has a similar structure including a substrate 232, an inter-connector 238 connecting the substrate 232 to the Cu-bond 241. The inter-connector 238 may include multiple metal layers, vias and contacts (not shown). Outside signals and power supplies are connected to the top die 230. In a typical process, a through-silicon-via (TSV) 252 is used to connect the inter-connector 238 to a back-side metal (MB) 255. Then an Aluminum pad (AP) 260, typically in a form of redistributed-layer (RDL) is deposited on top of the MB 255. A bonding wire can be attached to the AP 260 at a bump 265.
Referring to both FIGS. 1 and 2, a skilled artisan would recognize that the conventional I/O cell pad 100 can not be used for 3D IC pad structure 200, as the TSV 252 and the inter-connector 238 prevents any I/O cell structure to be placed underneath the AP 260. A chip with I/O pad structure designed in a conventional way, as shown in FIG. 1, can not simply be flipped over and used for 3D ICs. As I/O cell structure is very critical and may require proven-in-silicon, redesigning an I/O cell structure for fit for 3D ICs is often time not practical and economical.
As such, what is desired is a structure that can adopt the conventional I/O pad structure to be used in 3D ICs without redesigning the conventional I/O pad structure.